Method of making moisture barrier for bond pads and integrated circuit having the same

ABSTRACT

A semiconductor die includes a substrate layer, one or more metal layers disposed over the substrate layer, and a pair of polyimide layers disposed over the substrate so that they define an interface therebetween. One or both of the pair of polyimide layers have a trench that separates the interface from the one or more metal layers. The trench can be formed by etching the polyimide layer(s). A topcoat insulation layer is disposed over the one or more metal layers and polyimide layers. The topcoat insulation layer is impervious to moisture and the trench inhibits migration of moisture along the interface to the one or more metal layers, thereby preventing metal migration from the one or more metal layers along the interface.

INCORPORATION BY REFERENCE TO ANY PRIORITY APPLICATIONS

Any and all applications for which a foreign or domestic priority claimis identified in the Application Data Sheet as filed with the presentapplication are hereby incorporated by reference under 37 CFR 1.57.

BACKGROUND Field

The present disclosure is directed to a moisture barrier for use betweenbond pads and other components in an integrated circuit, and moreparticularly to a moisture barrier for use between bond pads and othercomponents in integrated circuits that use a polyimide interlayerinsulator.

Description of the Related Art

Some semiconductor integrated circuits (ICs) use polyimide as aninterlayer insulator. However, during operation under ambientconditions, as well as during high accelerated stress testing (HAST)test conditions (high temperature, high pressure, high moistureconditions), polyimide acts as a wick to draw moisture from outside andtransport it to sensitive elements on the ICs, such as bond pads thatare used for high voltage and are near die edges or close to othercomponents that are low voltage. In the presence of moisture, metalmigration between bond pads and other components (e.g., other bond pads,capacitors) has been seen to cause a short circuit (e.g., in productsthat use gold-based metallization and polyimide based isolation betweenmetal layers). Such moisture primarily travels along an interfacebetween adjacent polyimide layers.

SUMMARY

Accordingly, there is a need for an improved manner to avoid moistureexposure to bond pads that can cause metal migration between the bondpads or between a bond pad and another component (e.g., a capacitor),that can lead to a short circuit, such as in semiconductor integratedcircuits that use polyimide as an interlayer insulator.

In accordance with one aspect of the invention, a packaged module isprovided with a moat (e.g., a no polyimide zone) proximate that providesa moisture barrier. In one implementation, the moat is provided aroundone or more bond pads (e.g., provided around each bond pad).

In accordance with one aspect of the disclosure, a semiconductor die isprovided. The semiconductor die comprises a substrate layer and one ormore metal layers disposed over the substrate layer. The semiconductordie also comprises a first polymer interlevel dielectric layer and asecond polymer interlevel dielectric layer disposed over the substrate,at least one of the first and second polymer interlevel dielectriclayers spaced from (e.g., laterally spaced from) the one or more metallayers by a trench so that an interface between the first and secondpolymer interlevel dielectric layers is spaced apart from the one ormore metal layers. The semiconductor die also comprises a topcoatinsulation layer disposed over the one or more metal layers and one ormore polymer interlevel dielectric layers. The top coat insulation layeris impervious to moisture and the trench inhibits migration of moisturealong the interface to the one or more metal layers, thereby preventingmetal migration from the one or more metal layers along the interface.

In accordance with another aspect of the disclosure, a radiofrequencymodule is provided. The radiofrequency module comprises a printedcircuit board. The radiofrequency module also comprises a semiconductordie mounted on the printed circuit board. The semiconductor diecomprises a substrate layer and one or more metal layers disposed overthe substrate layer. The semiconductor die also comprises a firstpolymer interlevel dielectric layer and a second polymer interleveldielectric layer disposed over the substrate, at least one of the firstand second polymer interlevel dielectric layers spaced from (e.g.,laterally spaced from) the one or more metal layers by a trench so thatan interface between the first and second polymer interlevel dielectriclayers is spaced apart from the one or more metal layers. Thesemiconductor die also comprises a topcoat insulation layer disposedover the one or more metal layers and one or more polymer interleveldielectric layers. The top coat insulation layer is impervious tomoisture and the trench inhibits migration of moisture along theinterface to the one or more metal layers, thereby preventing metalmigration from the one or more metal layers along the interface.

In accordance with another aspect of the disclosure, a wireless mobiledevice is provided. The wireless mobile device comprises one or moreantennas, a front end system that communicates with the one or moreantennas, and a semiconductor die. The semiconductor die comprises asubstrate layer and one or more metal layers disposed over the substratelayer. The semiconductor die also comprises a first polymer interleveldielectric layer and a second polymer interlevel dielectric layerdisposed over the substrate, at least one of the first and secondpolymer interlevel dielectric layers spaced from (e.g., laterally spacedfrom) the one or more metal layers by a trench so that an interfacebetween the first and second polymer interlevel dielectric layers isspaced apart from the one or more metal layers. The semiconductor diealso comprises a topcoat insulation layer disposed over the one or moremetal layers and one or more polymer interlevel dielectric layers. Thetop coat insulation layer is impervious to moisture and the trenchinhibits migration of moisture along the interface to the one or moremetal layers, thereby preventing metal migration from the one or moremetal layers along the interface.

In accordance with another aspect of the disclosure, a method of makinga semiconductor die is provided. The method comprises forming orproviding a substrate layer, and forming or applying one or more metallayers over the substrate layer. The method also comprises forming orapplying a first polymer interlevel dielectric layer over the substratelayer and forming or applying a second polymer interlevel dielectriclayer over the first polymer interlevel dielectric layer to define aninterface therebetween. At least a portion of the first and secondpolymer interlevel dielectric layers are adjacent at least one of theone or more metal layers. The method also comprises forming a trench inthe one or both of the first and second polymer interlevel dielectriclayers and filling the trench such that the interface between the firstand second polymer interlevel dielectric layers is separated from (e.g.,laterally separated from) the one or more metal layers. The method alsocomprises forming or applying a topcoat insulation layer over the one ormore metal layers and first and second polymer interlevel dielectriclayers, the topcoat insulation layer being impervious to moisture. Thetrench inhibits migration of moisture along the interface to the one ormore metal layers, thereby preventing metal migration from the one ormore metal layers along the interface.

In accordance with another aspect of the disclosure, a method of makinga radiofrequency module is provided. The method comprises forming orproviding a printed circuit board that includes a substrate layer. Themethod also comprises forming or providing a semiconductor die. Formingor providing the semiconductor die comprises forming or providing asubstrate layer, and forming or applying one or more metal layers overthe substrate layer. Forming or providing the semiconductor die alsocomprises forming or applying a first polymer interlevel dielectriclayer over the substrate layer and forming or applying a second polymerinterlevel dielectric layer over the first polymer interlevel dielectriclayer to define an interface therebetween. At least a portion of thefirst and second polymer interlevel dielectric layers are adjacent atleast one of the one or more metal layers. Forming or providing thesemiconductor die also comprises forming a trench in the one or both ofthe first and second polymer interlevel dielectric layers and fillingthe trench such that the interface between the first and second polymerinterlevel dielectric layers is separated from (e.g., laterallyseparated from) the one or more metal layers. Forming or providing thesemiconductor die also comprises forming or applying a topcoatinsulation layer over the one or more metal layers and first and secondpolymer interlevel dielectric layers, the topcoat insulation layer beingimpervious to moisture. The trench inhibits migration of moisture alongthe interface to the one or more metal layers, thereby preventing metalmigration from the one or more metal layers along the interface. Themethod also comprises mounting the semiconductor die on the printedcircuit board.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of one embodiment of a wireless device.

FIG. 2A is a schematic diagram of one embodiment of a packaged module.

FIG. 2B is a schematic diagram of a cross-section of the packaged moduleof FIG. 2A taken along the lines 2B-2B.

FIG. 3A is a schematic cross-sectional side view of a conventional diewith a bond pad.

FIG. 3B is a schematic cross-sectional side view of a conventional diewith a pair of bond pads.

FIG. 4 is a schematic cross-sectional side view of a die having a bondpad with a moisture barrier.

FIG. 5 is a schematic cross-sectional side view of a die having a bondpad with a moisture barrier.

FIG. 6 is a schematic cross-sectional side view of a die having a bondpad with a moisture barrier.

FIG. 7 is a schematic cross-sectional side view of a die having a bondpad with a moisture barrier.

FIG. 8A is a schematic cross-sectional side view of a die having a bondpad with a moisture barrier.

FIG. 8B is a schematic cross-sectional side view of a die having a pairof bond pads with a moisture barrier.

FIG. 9 is a schematic cross-sectional side view of a die having a bondpad with a moisture barrier.

FIG. 10 is a schematic cross-sectional side view of a die having a bondpad with a moisture barrier.

FIG. 11 is a schematic cross-sectional side view of a die having a bondpad with a moisture barrier.

FIG. 12 is a block diagram of a method for manufacturing a die withbarrier in one or more polymer layers and a bond pad with a moisturebarrier.

DETAILED DESCRIPTION

The following detailed description of certain embodiments presentsvarious descriptions of specific embodiments. However, the innovationsdescribed herein can be embodied in a multitude of different ways, forexample, as defined and covered by the claims. In this description,reference is made to the drawings were like reference numerals canindicate identical or functionally similar elements. It will beunderstood that elements illustrated in the figures are not necessarilydrawn to scale. Moreover, it will be understood that certain embodimentscan include more elements than illustrated in a drawing and/or a subsetof the elements illustrated in a drawing. Further, some embodiments canincorporate any suitable combination of features from two or moredrawings.

The International Telecommunication Union (ITU) is a specialized agencyof the United Nations (UN) responsible for global issues concerninginformation and communication technologies, including the shared globaluse of radio spectrum.

The 3rd Generation Partnership Project (3GPP) is a collaboration betweengroups of telecommunications standard bodies across the world, such asthe Association of Radio Industries and Businesses (ARIB), theTelecommunications Technology Committee (TTC), the China CommunicationsStandards Association (CCSA), the Alliance for TelecommunicationsIndustry Solutions (ATIS), the Telecommunications Technology Association(TTA), the European Telecommunications Standards Institute (ETSI), andthe Telecommunications Standards Development Society, India (TSDSI).

Working within the scope of the ITU, 3GPP develops and maintainstechnical specifications for a variety of mobile communicationtechnologies, including, for example, second generation (2G) technology(for instance, Global System for Mobile Communications (GSM) andEnhanced Data Rates for GSM Evolution (EDGE)), third generation (3G)technology (for instance, Universal Mobile Telecommunications System(UMTS) and High Speed Packet Access (HSPA)), and fourth generation (4G)technology (for instance, Long Term Evolution (LTE) and LTE-Advanced).

The technical specifications controlled by 3GPP can be expanded andrevised by specification releases, which can span multiple years andspecify a breadth of new features and evolutions.

In one example, 3GPP introduced carrier aggregation (CA) for LTE inRelease 10. Although initially introduced with two downlink carriers,3GPP expanded carrier aggregation in Release 14 to include up to fivedownlink carriers and up to three uplink carriers. Other examples of newfeatures and evolutions provided by 3GPP releases include, but are notlimited to, License Assisted Access (LAA), enhanced LAA (eLAA),Narrowband Internet-of-Things (NB-IOT), Vehicle-to-Everything (V2X), andHigh Power User Equipment (HPUE).

3GPP introduced Phase 1 of fifth generation (5G) technology in Release15 and plans to introduce Phase 2 of 5G technology in Release 16(targeted for 2019). Subsequent 3GPP releases will further evolve andexpand 5G technology. 5G technology is also referred to herein as 5G NewRadio (NR).

5G NR supports or plans to support a variety of features, such ascommunications over millimeter wave spectrum, beam forming capability,high spectral efficiency waveforms, low latency communications, multipleradio numerology, and/or non-orthogonal multiple access (NOMA). Althoughsuch RF functionalities offer flexibility to networks and enhance userdata rates, supporting such features can pose a number of technicalchallenges.

The teachings herein are applicable to a wide variety of communicationsystems, including, but not limited to, analog devices, radiofrequencydevices, and communication systems using advanced cellular technologies,such as LTE-Advanced, LTE-Advanced Pro, and/or 5G NR.

FIG. 1 is a schematic diagram of one embodiment of a wireless device100. The wireless device 100 can be, for example but not limited to, aportable telecommunication device such as a mobile cellular-typetelephone. The wireless device 100 can include one or more of a basebandsystem 101, a transceiver 102, a front end system 103, one or moreantennas 104, a power management system 105, a memory 106, a userinterface 107, a battery 108 (e.g., direct current (DC) battery). Otheradditional components, such as a speaker, display and keyboard canoptionally be connected to the baseband system 101. The battery 108 canprovide power to the wireless device 100.

It should be noted that, for simplicity, only certain components of thewireless device 100 are illustrated herein. The control signals providedby the baseband system 101 control the various components within thewireless device 100. Further, the function of the transceiver 102 can beintegrated into separate transmitter and receiver components.

The wireless device 100 can be used communicate using a wide variety ofcommunications technologies, including, but not limited to, 2G, 3G, 4G(including LTE, LTE-Advanced, and LTE-Advanced Pro), 5G NR, WLAN (forinstance, Wi-Fi), WPAN (for instance, Bluetooth and ZigBee), WMAN (forinstance, WiMax), and/or GPS technologies.

The transceiver 102 generates RF signals for transmission and processesincoming RF signals received from the antennas 104. It will beunderstood that various functionalities associated with the transmissionand receiving of RF signals can be achieved by one or more componentsthat are collectively represented in FIG. 1 as the transceiver 102. Inone example, separate components (for instance, separate circuits ordies) can be provided for handling certain types of RF signals.

The front end system 103 aids in conditioning signals transmitted toand/or received from the antennas 104. In the illustrated embodiment,the front end system 103 includes one or more power amplifiers (PAs)111, low noise amplifiers (LNAs) 112, filters 113, switches 114,duplexers 115 and capacitors 300. However, other implementations arepossible.

For example, the front end system 103 can provide a number offunctionalities, including, but not limited to, amplifying signals fortransmission, amplifying received signals, filtering signals, switchingbetween different bands, switching between different power modes,switching between transmission and receiving modes, duplexing ofsignals, multiplexing of signals (for instance, diplexing ortriplexing), or some combination thereof.

In certain implementations, the wireless device 100 supports carrieraggregation, thereby providing flexibility to increase peak data rates.Carrier aggregation can be used for both Frequency Division Duplexing(FDD) and Time Division Duplexing (TDD), and may be used to aggregate aplurality of carriers or channels. Carrier aggregation includescontiguous aggregation, in which contiguous carriers within the sameoperating frequency band are aggregated. Carrier aggregation can also benon-contiguous, and can include carriers separated in frequency within acommon band or in different bands.

The antennas 104 can include antennas used for a wide variety of typesof communications. For example, the antennas 104 can include antennasfor transmitting and/or receiving signals associated with a wide varietyof frequencies and communications standards.

In certain implementations, the antennas 104 support MIMO communicationsand/or switched diversity communications. For example, MIMOcommunications use multiple antennas for communicating multiple datastreams over a single radio frequency channel. MIMO communicationsbenefit from higher signal to noise ratio, improved coding, and/orreduced signal interference due to spatial multiplexing differences ofthe radio environment. Switched diversity refers to communications inwhich a particular antenna is selected for operation at a particulartime. For example, a switch can be used to select a particular antennafrom a group of antennas based on a variety of factors, such as anobserved bit error rate and/or a signal strength indicator.

The wireless device 100 can operate with beamforming in certainimplementations. For example, the front end system 103 can include phaseshifters having variable phase controlled by the transceiver 102.Additionally, the phase shifters are controlled to provide beamformation and directivity for transmission and/or reception of signalsusing the antennas 104. For example, in the context of signaltransmission, the phases of the transmit signals provided to theantennas 104 are controlled such that radiated signals from the antennas104 combine using constructive and destructive interference to generatean aggregate transmit signal exhibiting beam-like qualities with moresignal strength propagating in a given direction. In the context ofsignal reception, the phases are controlled such that more signal energyis received when the signal is arriving to the antennas 104 from aparticular direction. In certain implementations, the antennas 104include one or more arrays of antenna elements to enhance beamforming.

The baseband system 101 is coupled to the user interface 107 tofacilitate processing of various user input and output (I/O), such asvoice and data. The baseband system 101 provides the transceiver 102with digital representations of transmit signals, which the transceiver102 processes to generate RF signals for transmission. The basebandsystem 101 also processes digital representations of received signalsprovided by the transceiver 102. As shown in FIG. 1, the baseband system101 is coupled to the memory 106 of facilitate operation of the wirelessdevice 100.

The memory 106 can be used for a wide variety of purposes, such asstoring data and/or instructions to facilitate the operation of thewireless device 100 and/or to provide storage of user information.

The power management system 105 provides a number of power managementfunctions of the wireless device 100. In certain implementations, thepower management system 105 includes a PA supply control circuit thatcontrols the supply voltages of the power amplifiers 111. For example,the power management system 105 can be configured to change the supplyvoltage(s) provided to one or more of the power amplifiers 111 toimprove efficiency, such as power added efficiency (PAE).

As shown in FIG. 1, the power management system 105 receives a batteryvoltage from the battery 108. The battery 108 can be any suitablebattery for use in the wireless device 100, including, for example, alithium-ion battery.

FIG. 2A is a schematic diagram of one embodiment of a packaged module200. FIG. 2B is a schematic diagram of a cross-section of the packagedmodule 200 of FIG. 2A taken along the lines 2B-2B.

The packaged module 200 includes radio frequency components 201, asemiconductor die 202, surface mount devices 203, wirebonds 208, apackage substrate 230, an encapsulation structure 240, and one or morecapacitors 300. The package substrate 230 includes pads (e.g., bondpads) 206 formed from conductors disposed therein. Additionally, thesemiconductor die 202 includes pins or pads (e.g., bond pads) 204, andthe wirebonds 208 have been used to connect the pads (e.g., bond pads)204 of the die 202 to the pads (e.g., bond pads) 206 of the packagesubstrate 220.

The semiconductor die 202 includes a power amplifier 245, which can beimplemented in accordance with one or more features disclosed herein.

The packaging substrate 230 can be configured to receive a plurality ofcomponents such as radio frequency components 201, the semiconductor die202 and the surface mount devices 203, which can include, for example,surface mount capacitors and/or inductors. In one implementation, theradio frequency components 201 include integrated passive devices(IPDs).

As shown in FIG. 2B, the packaged module 200 is shown to include aplurality of contact pads 232 disposed on the side of the packagedmodule 200 opposite the side used to mount the semiconductor die 202.Configuring the packaged module 200 in this manner can aid in connectingthe packaged module 200 to a circuit board, such as a phone board of amobile device. The example contact pads 232 can be configured to provideradio frequency signals, bias signals, and/or power (for example, apower supply voltage and ground) to the semiconductor die 202 and/orother components. As shown in FIG. 2B, the electrical connectionsbetween the contact pads 232 and the semiconductor die 202 can befacilitated by connections 233 through the package substrate 230. Theconnections 233 can represent electrical paths formed through thepackage substrate 220, such as connections associated with vias andconductors of a multilayer laminated package substrate.

In some embodiments, the packaged module 200 can also include one ormore packaging structures to, for example, provide protection and/orfacilitate handling. Such a packaging structure can include overmold orencapsulation structure 240 formed over the packaging substrate 230 andthe components and die(s) disposed thereon.

It will be understood that although the packaged module 200 is describedin the context of electrical connections based on wirebonds, one or morefeatures of the present disclosure can also be implemented in otherpackaging configurations, including, for example, flip-chipconfigurations.

FIG. 3A schematically illustrates a conventional die 202A with a bondpad 204A. The die 202A includes a substrate layer 510A. Optionally, thesubstrate layer 510A can be made of gallium arsenide (GaAs). One or moreinsulation layers 520A are disposed over (e.g., directly over, adjacent)the substrate layer 510A. Optionally, the insulation layer 520A can bemade of silicon nitride (SiN).

A first metal layer 530A (M1) can be disposed over (e.g., directly over,adjacent) at least a portion of the insulation layer 520A. The firstmetal layer 530A can define a first electrode portion of the bond pad204A and extend along a length smaller than a length of the insulationlayer 520A. A second insulation layer 540A can be disposed over (e.g.,directly over, adjacent) the first metal layer 530A and disposed overthe insulation layer 520A. The second insulation layer 540A canoptionally be made of silicon nitride. A third insulation layer 545A canbe disposed over (e.g., directly over, adjacent) the second insulationlayer 540A. The third insulation layer 545A can optionally be made ofsilicon nitride.

A second metal layer 550A (M2) can be disposed over at least a portionof (e.g., less than an entire length of) the second insulation layer540A and third insulation layer 545A. The second metal layer 550A candefine a second electrode portion of the bond pad 204A and contact atleast a portion of the first metal layer 530A (M1). The second metallayer 550A can be longer than the first metal layer 530A. A firstinterlayer insulator layer 570A (V1) is disposed over (e.g., directlyover, adjacent) the third insulation layer 545A and extend under atleast a portion of the second metal layer 550A (M2). The firstinterlayer insulator layer 560A can be made of polyimide. However, thefirst interlayer insulator layer 560A can be made of other suitablepolymer materials.

A third metal layer 570A (M3) can be disposed over (e.g., directly over,adjacent) at least a portion of the second metal layer 550A. The thirdmetal layer 570A can extend along a length greater than the length ofthe second metal layer 550A. A second interlayer insulator layer 580A(V2) can be disposed over (e.g., directly over, adjacent) the firstinterlayer insulator layer 560A, and extend in between at least aportion of the second metal layer 550A and third metal layer 570A. Thesecond interlayer insulator layer 580A can be made of polyimide.However, the second interlayer insulator layer 580A can be made of othersuitable polymer materials. A topcoat insulation layer (or fourthinsulation layer) 590A can be disposed over (e.g. directly over,adjacent) at least a portion of the second interlayer insulator layer580A and at last a portion of the third metal layer 570A. The topcoatinsulation layer 590A can optionally be made of silicon nitride, and isimpervious to moisture, thereby providing a moisture barrier. The bondpad 204A can be defined by at least a portion of one or more of thefirst, second and third metal layers 530A, 550A, 570A.

FIG. 3B schematically illustrates a conventional die 202B with a firstbond pad 204B1 and a second bond pad 204B1. The features of the die 202Bare similar to the features of the die 202A, and the features of thebond pads 204B1, 204B2 are similar to the features of the bond pad 204Ain FIG. 3A. Thus, reference numerals used to designate the variouscomponents of the die 202B and bond pads 204B1, 204B2 are similar tothose used for identifying the corresponding components of the die 202Aand bond pad 204A in FIG. 3A, except that a “B” instead of an “A” hasbeen added to the numerical identifier. Therefore, the structure anddescription for the various features of the die 202A and bond pad 204Ain FIG. 3A are understood to also apply to the corresponding features ofthe die 202B and bond pads 204B1, 204B2, except as described below.

The die 202B differs from the die 202A in that it includes two bond pads204B1, 204B2 instead of one bond pad 204A. The first and secondinterlayer insulation layers 560B, 580B, like the first and secondinterlayer insulation layers 560A, 580A, define an interface or junctionI into which moisture can migrate (e.g., from defects on a top portionor edges of the die 202A, 202B, from flaws in the bond pads 204A, 204B).The presence of moisture in the interface I in the presence of anelectric voltage (via the bond pads 204A, 204B) can cause migration ofmetal (e.g., gold) along the interface I from one bond pad 204B1 toanother bond pad 204B2 (or to another component of the die 202B),causing a short circuit.

Moisture Barrier

FIG. 4 schematically illustrates a die 202C with a bond pad 204C. Thefeatures of the die 202C are similar to the features of the die 202A,and the features of the bond pad 204C are similar to the features of thebond pad 204A in FIG. 3A. Thus, reference numerals used to designate thevarious components of the die 202C and bond pad 204C are similar tothose used for identifying the corresponding components of the die 202Aand bond pad 204A in FIG. 3A, except that a “C” instead of an “A” hasbeen added to the numerical identifier. Therefore, the structure anddescription for the various features of the die 202A and bond pad 204Ain FIG. 3A are understood to also apply to the corresponding features ofthe die 202C and bond pad 204C, except as described below.

The die 202C includes a substrate layer 510C. Optionally, the substratelayer 510C can be made of gallium arsenide (GaAs). An insulation layer520C is disposed over (e.g., directly over, adjacent) the substratelayer 510C. Optionally, the insulation layer 520C can be made of siliconnitride (SiN).

A first metal layer 530C (M1) can be disposed over (e.g., directly over,adjacent) at least a portion of the insulation layer 520C. The firstmetal layer 530C can define a first electrode portion of the bond pad204C and extend along a length smaller than a length of the insulationlayer 520C. A second insulation layer 540C can be disposed over (e.g.,directly over, adjacent) at least a portion of the insulation layer520C. The second insulation layer 540C can optionally be made of siliconnitride.

A second metal layer 550C (M2) can be disposed over at least a portionof (e.g., less than an entire length of) the first metal layer 530C. Thesecond metal layer 550C can define a second electrode portion of thebond pad 204C and optionally extend along a length smaller than a lengthof the first metal layer 530C. A third insulation layer 545C can bedisposed over at least a portion of (e.g., less than an entire lengthof) the second insulation layer 540C. A first interlayer insulator layer560C (V1) is disposed over (e.g., directly over, adjacent) the thirdinsulation layer 545C. The first interlayer insulator layer 560C can bemade of polyimide. However, the first interlayer insulator layer 560Ccan be made of other suitable polymer materials. The first insulatorlayer 560C does not extend to the first and second metal layers 530C,550C, as further discussed below.

A third metal layer 570C (M3) can be disposed over (e.g., directly over,adjacent) at least a portion of (e.g., less than an entire length of)the second metal layer 550C. The third metal layer 570C can define athird electrode portion of the bond pad 204C and extend along a lengthgreater than the length of the first metal layer 530C and the secondmetal layer 550C. A second interlayer insulator layer 580C (V2) can bedisposed over (e.g., directly over, adjacent) the first interlayerinsulator layer 560C, in contact with the first and second metal layers530C, 550C, and at least partially between the second metal layer 550Cand the third metal layer 570C. The second interlayer insulator layer580C can be made of polyimide. However, the second interlayer insulatorlayer 580C can be made of other suitable polymer materials. A topcoatinsulation layer (or fourth insulation layer) 590C can be disposed over(e.g. directly over, adjacent) the third metal layer 570C and the secondinterlayer insulator layer 580C. The topcoat insulation layer 590C canoptionally be made of silicon nitride, and is impervious to moisture,thereby providing a moisture barrier.

Advantageously, only the second interlayer insulator layer 580C contactsthe first, second and third metal layers 530C, 550C, 570C, therebyproviding the die 202C with a moisture barrier. The first interlayerinsulator layer 560C is etched to define a trench T so that the firstinterlayer insulator layer 560C terminates before (e.g., approximately 4microns away from) reaching the metal layers 530C, 550C, 570C and thesecond interlayer insulator layer 580C fills the trench T left by theportion of the first interlayer insulator layer 560C that is etchedaway. Accordingly, the interface I between the first and secondinterlayer insulator layers 560C, 580C does not extend to the first,second or third metal layers 530C, 550C, 570C, thereby preventingmoisture migration, as well as metal migration when exposed to avoltage, between the bond pad 204C and other components (e.g., anotherbond pad, another component of the die) along the interface I. Theopening O of the bond pad 204C (e.g., exposed portion of the third metallayer 570C), in one implementation, is approximately 50 microns.

With reference to FIG. 4, the first, second and third insulation layers520C, 540C, 545C are also etched and filled with the second interlayerinsulator layer 580C. In another implementation, only the second andthird insulation layers 540C, 545C are etched. In anotherimplementation, only the third insulation layer 545C is etched.

FIG. 5 schematically illustrates a die 202D with a bond pad 204D. Thefeatures of the die 202D are similar to the features of the die 202C,and the features of the bond pad 204D are similar to the features of thebond pad 204C in FIG. 4. Thus, reference numerals used to designate thevarious components of the die 202D and bond pad 204D are similar tothose used for identifying the corresponding components of the die 202Cand bond pad 204C in FIG. 4, except that a “D” instead of an “C” hasbeen added to the numerical identifier. Therefore, the structure anddescription for the various features of the die 202C and bond pad 204Cin FIG. 4 are understood to also apply to the corresponding features ofthe die 202D and bond pad 204D, except as described below.

The die 202D and bond pad 204D differ from the die 202C and bond pad204C in that the first metal layer 530D extends between the firstinsulation layer 520D and the second insulation layer 540D and acrossthe die 202D, thereby allowing an electrical communication between thebond pad 204D and another component (e.g., bond pad, capacitor, etc.) ofthe die 202D. The first interlayer insulator layer 560D is etched todefine a trench T so that the first interlayer insulator layer 560Dterminates before (e.g., approximately 4 microns away from) reaching thesecond and third metal layers 550D, 570D), and the second interlayerinsulator layer 580D fills the trench T. Accordingly, the interface Ibetween the first and second interlayer insulator layers 560D, 580D doesnot reach the metal layer 550D, 570D, which prevents moisture migrationalong the interface I, thereby preventing metal migration (via theinterface I) when a voltage is applied. The first metal layer 530Dextends over the first insulation layer 520D, and under at least aportion of the second interlayer insulator layer 580D (that fills thetrench) and under the second insulation layer 540D.

FIG. 6 schematically illustrates a die 202E with a bond pad 204E. Thefeatures of the die 202E are similar to the features of the die 202D,and the features of the bond pad 204E are similar to the features of thebond pad 204D in FIG. 5. Thus, reference numerals used to designate thevarious components of the die 202E and bond pad 204E are similar tothose used for identifying the corresponding components of the die 202Dand bond pad 204D in FIG. 5, except that a “E” instead of an “D” hasbeen added to the numerical identifier. Therefore, the structure anddescription for the various features of the die 202D and bond pad 204Din FIG. 5 are understood to also apply to the corresponding features ofthe die 202E and bond pad 204E, except as described below.

The die 202E and bond pad 204E differ from the die 202D and bond pad204D in that the first metal layer 530E does not extend entirely acrossthe die 202E, but is instead bounded by the first insulation layer 520Eon a bottom thereof, the second and third insulation layers 540E, 545Eon an end thereof and the second metal layer 550E on a top thereof. Thesecond metal layer 550E extends across the die 202E between the firstmetal layer 530E and the first interlayer insulator layer 560E on abottom thereof, and the third metal layer 570E and the second interlayerinsulator layer 580E on a top thereof. The second metal layer 550Etherefore allows an electrical communication between the bond pad 204Eand another component (e.g., bond pad, capacitor, etc.) of the die 202E.The first interlayer insulator layer 560E is etched to define a trenchT, and the second metal layer 550E fills the trench T. Additionally,because the second metal layer 550E is interposed between the first andsecond interlayer insulator layers 560E, 580E, there is no interfacebetween the first and second interlayer insulator layers 560E, 580E,which prevents moisture migration, thereby preventing metal migration(via the interface) when a voltage is applied. The first metal layer530E is shorter than the second metal layer 550E but longer than thethird metal layer 570E. The second interlayer insulator layer 580Eextends at least partially in between the second and third metal layers550E, 570E.

FIG. 7 schematically illustrates a die 202F with a bond pad 204F. Thefeatures of the die 202F are similar to the features of the die 202C,and the features of the bond pad 204F are similar to the features of thebond pad 204C in FIG. 4. Thus, reference numerals used to designate thevarious components of the die 202F and bond pad 204F are similar tothose used for identifying the corresponding components of the die 202Cand bond pad 204C in FIG. 4, except that an “F” instead of an “C” hasbeen added to the numerical identifier. Therefore, the structure anddescription for the various features of the die 202C and bond pad 204Cin FIG. 4 are understood to also apply to the corresponding features ofthe die 202F and bond pad 204F, except as described below.

The die 202F and bond pad 204F differ from the die 202C and bond pad204C in that the third metal layer 570E extends between the secondinterlayer insulator layer 280F and the topcoat insulation layer 590Fand across the die 202D, thereby allowing an electrical communicationbetween the bond pad 204F and another component (e.g., bond pad,capacitor, etc.) of the die 202F. The first interlayer insulator layer560F is etched to define a trench T so that the first interlayerinsulator layer 560F terminates before (e.g., approximately 4 micronsaway from) reaching the first and second metal layers 530F, 550F), andthe second interlayer insulator layer 580F fills the trench T.Accordingly, the interface I between the first and second interlayerinsulator layers 560F, 580F does not reach the metal layers 530F, 550F,which prevents moisture migration along the interface I, therebypreventing metal migration (via the interface I) when a voltage isapplied.

FIG. 8A schematically illustrates a die 202G with a bond pad 204G. Thefeatures of the die 202G are similar to the features of the die 202F,and the features of the bond pad 204G are similar to the features of thebond pad 204F in FIG. 7. Thus, reference numerals used to designate thevarious components of the die 202G and bond pad 204G are similar tothose used for identifying the corresponding components of the die 202Fand bond pad 204F in FIG. 7, except that a “G” instead of an “F” hasbeen added to the numerical identifier. Therefore, the structure anddescription for the various features of the die 202F and bond pad 204Fin FIG. 7 are understood to also apply to the corresponding features ofthe die 202G and bond pad 204G, except as described below.

The die 202G and bond pad 204G differ from the die 202F and bond pad204F in that the second interlayer insulator layer 580G terminatesbefore (e.g., approximately 4 microns away from) reaching the first,second and third metal layers 530G, 550G, 570G. The first and secondinterlayer insulator layers 560G, 580G are etched to define a trench Tand the topcoat insulation layer 590G extends into the trench T andbounds (e.g., at least partially fills the trench and bounds) the firstand second interlayer insulator layers 560G, 580G apart from the metallayers 530G, 550G, 570G (e.g., which are also at least partially boundedor circumscribed by the topcoat insulation layer 590G that extends intothe trench T). The topcoat insulation layer 590G provides a moisturebarrier around the metal layers 530G, 550G, 570G, and around the firstand second interlayer insulator layers 560G, 580G, thereby preventingmoisture migration, and therefore metal migration when under a voltage,between the metal layers 530G, 550G, 570G of the bond pad 204G and theinterlayer insulator layers 560G, 580G along the interface I.

With continued reference to FIG. 8A, the third metal layer 570G isshorter than the second metal layer 550G, which is shorter than thefirst metal layer 530G. As shown in FIG. 8A, the first, second and thirdinsulation layers 520G, 540G, 545G are also etched to define at least aportion of the trench T, which is then bounded (e.g., at least partiallyfilled) with the topcoat insulation layer 590G. In anotherimplementation, only the second and third insulation layers 540G, 545Gare etched. In another implementation, only the third insulation layer545G is etched.

FIG. 8B schematically illustrates a die 202H with a first bond pad 204H1and a second bond pad 204H2. The features of the die 202H are similar tothe features of the die 202G, and the features of the bond pad(s) 204H1,204H2 are similar to the features of the bond pad 204G in FIG. 8A. Thus,reference numerals used to designate the various components of the die202H and bond pad(s) 204H1, 204H2 are similar to those used foridentifying the corresponding components of the die 202G and bond pad204G in FIG. 8A, except that an “H” instead of a “G” has been added tothe numerical identifier. Therefore, the structure and description forthe various features of the die 202G and bond pad 204G in FIG. 8A areunderstood to also apply to the corresponding features of the die 202Hand bond pad(s) 204H1, 204H2, except as described below.

The die 202H and bond pad(s) 204H1, 204H2 differ from the die 202G andbond pad 204G in that there are two bond pad(s) 204H1, 204H2 closetogether (e.g., less than about 4 microns apart), each substantiallyidentical to the bond pad 204G in FIG. 8A, and the first and secondinterlayer insulator layers are excluded. As shown in FIG. 8B, thetrench T is defined between the bond pads 204H1, 204H2, and the topcoatinsulation layer 590H extends into the trench T and bounds (e.g., atleast partially fills the trench and bounds) the metal layers 530H1,550H1, 570H1 of the first bond pad 204H1 apart from the metal layers530H2, 550H2, 570H2 of the second bond pad 204H2 (e.g., which are alsoat least partially bounded or circumscribed by the topcoat insulationlayer 590H that extends into the trench T). The topcoat insulation layer590H provides a moisture barrier around the metal layers 530H1/530H2,550H1/550H2, 570H1/570H2 of the bond pads 204H1, 204H2, therebypreventing moisture migration, and therefore metal migration when undera voltage, between bond pads 204H1, 204H2.

FIG. 9 schematically illustrates a die 202J with a bond pad 204J. Thefeatures of the die 202J are similar to the features of the die 202G,and the features of the bond pad 204J are similar to the features of thebond pad 204G in FIG. 8A. Thus, reference numerals used to designate thevarious components of the die 202J and bond pad 204J are similar tothose used for identifying the corresponding components of the die 202Gand bond pad 204G in FIG. 8A, except that an “J” instead of a “G” hasbeen added to the numerical identifier. Therefore, the structure anddescription for the various features of the die 202G and bond pad 204Gin FIG. 8A are understood to also apply to the corresponding features ofthe die 202J and bond pad 204J, except as described below.

The die 202J and bond pad 204J differ from the die 202G and bond pad204G in that the first metal layer 530J extends between the firstinsulation layer 520J and the second insulation layer 540J and acrossthe die 202J, thereby allowing an electrical communication between thebond pad 204J and another component (e.g., bond pad, capacitor, etc.) ofthe die 202J. The first and second interlayer insulator layers 560J,580J are etched to define a trench T so that the first and secondinterlayer insulator layers 560J, 580J terminate before (e.g.,approximately 4 microns away from) reaching the second and third metallayers 550J, 570J), and the topcoat insulation layer 590J bounds thefirst and second interlayer insulator layers 560J, 580J away from thesecond and third metal layers 550J, 570J (e.g., the topcoat insulationlayer 590J at least partially fills the trench T). Accordingly, theinterface I between the first and second interlayer insulator layers560J, 580J does not reach the metal layer 550J, 570J, which preventsmoisture migration along the interface I, thereby preventing metalmigration (via the interface I) when a voltage is applied. The firstmetal layer 530J extends over the first insulation layer 520J, and underat least a portion of the topcoat insulation layer 590J (that fills thetrench T).

FIG. 10 schematically illustrates a die 202K with a bond pad 204K. Thefeatures of the die 202K are similar to the features of the die 202J,and the features of the bond pad 204K are similar to the features of thebond pad 204J in FIG. 9. Thus, reference numerals used to designate thevarious components of the die 202K and bond pad 204K are similar tothose used for identifying the corresponding components of the die 202Jand bond pad 204J in FIG. 9, except that an “K” instead of a “J” hasbeen added to the numerical identifier. Therefore, the structure anddescription for the various features of the die 202J and bond pad 204Jin FIG. 9 are understood to also apply to the corresponding features ofthe die 202K and bond pad 204K, except as described below.

The die 202K and bond pad 204K differ from the die 202J and bond pad204J in that the first metal layer 530K does not extend entirely acrossthe die 202K, but is instead bounded by the first insulation layer 520Kon a bottom thereof, the second and third insulation layers 540K, 545Kon an end thereof and the second metal layer 550K on a top thereof. Thesecond metal layer 550K extends across the die 202K between the firstmetal layer 530K and the first interlayer insulator layer 560K on abottom thereof, and the third metal layer 570K, the topcoat insulationlayer 590K and the second interlayer insulator layer 580K on a topthereof. The second metal layer 550K therefore allows an electricalcommunication between the bond pad 204K and another component (e.g.,bond pad, capacitor, etc.) of the die 202K. The first interlayerinsulator layer 560K is etched to define a trench T, and the secondmetal layer 550K fills the trench T. Additionally, because the secondmetal layer 550K is interposed between the first and second interlayerinsulator layers 560K, 580K, there is no interface between the first andsecond interlayer insulator layers 560K, 580K, which prevents moisturemigration, thereby preventing metal migration (via such an interface)when a voltage is applied. The first metal layer 530K is shorter thanthe second metal layer 550K but longer than the third metal layer 570K.The second interlayer insulator layer 580K is also etched and the topcoat insulation layer 590K fills the etched space between the secondinterlayer insulator layer 580K and the third metal layer 570K.

FIG. 11 schematically illustrates a die 202L with a bond pad 204L. Thefeatures of the die 202L are similar to the features of the die 202K,and the features of the bond pad 204L are similar to the features of thebond pad 204K in FIG. 10. Thus, reference numerals used to designate thevarious components of the die 202L and bond pad 204L are similar tothose used for identifying the corresponding components of the die 202Kand bond pad 204K in FIG. 10, except that an “L” instead of a “K” hasbeen added to the numerical identifier. Therefore, the structure anddescription for the various features of the die 202K and bond pad 204Kin FIG. 10 are understood to also apply to the corresponding features ofthe die 202L and bond pad 204L, except as described below.

The die 202L and bond pad 204L differ from the die 202K and bond pad204K in that the second metal layer 530L does not extend entirely acrossthe die 202L, but is instead bounded by the first metal layer 530L andfirst interlayer insulator layer 560L on a bottom thereof, the secondinterlayer insulator layer 580L on an end thereof and the third metallayer 550L and the second interlayer insulator layer 580L on a topthereof. The third metal layer 570L extends across the die 202L betweenthe second metal layer 550L and the second interlayer insulator layer580L on a bottom thereof, and the topcoat insulation layer 590L on a topthereof. The third metal layer 570L therefore allows an electricalcommunication between the bond pad 204L and another component (e.g.,bond pad, capacitor, etc.) of the die 202L. The first interlayerinsulator layer 560L is etched to define a trench T, and the secondmetal layer 550L fills the trench T. The second interlayer insulatorlayer 580L is etched and the third metal layer 570L fills the etchedspaced in the second interlayer insulator layer 580L and then extendsover the second interlayer insulator layer 580L. Accordingly, theinterface I between the first and second interlayer insulator layers560L, 580L does not reach the third metal layer 570L, which preventsmoisture migration along the interface I, thereby preventing metalmigration (via the interface I) when a voltage is applied. The firstmetal layer 530L is shorter than the second metal layer 550L, which isshorter than the third metal layer 570L.

Method

FIG. 12 shows a method 700 of making a die with a trench in a polymerinterlevel dielectric layer, such as the die 202C-202L with trench T.The method 700 includes the step of forming or providing a substratelayer 710, such as the substrate layer 510C-510L described above. Themethod 700 also includes the step of forming or providing one or moremetal layers 730 over the substrate layer, such as the first metal layer530C-530L, second metal layer 550C-550L, and third metal layer570C-570L. The one or more metal layers can be deposited and patterned.Optionally, an insulation layer (e.g., silicon nitride layer) can beapplied at least partially over the substrate layer, such as insulationlayers 520C-520L, 540C-540L, 545C-545L. The method 700 also includesforming or applying one or more polymer interlevel dielectric layers(e.g., of polyimide) 750, such as interlayer insulator layers 560C-560L,580C-580L. Optionally, a pair of polymer interlevel dielectric layersare applied so that they define an interface therebetween. The pair ofpolymer interlevel dielectric layers can be cured so that they bond(e.g., stick to each other). Optionally, one or both of the pair ofpolymer interlevel dielectric layers are etched to define via holes viawhich a metal layer can be deposited that connects with an underlyingmetal layer (e.g., a via hole is etched in the second polymer interleveldielectric layer 580C-580L to deposit the third metal layer 570C-570L sothat it connects with the second metal layer 550C-550L).

The method includes forming 770 a trench T in one or more of theinterlayer insulator layers. Optionally, the material (e.g., polyimide)of the interlayer insulator layers is etched to form the trench. Thetrench can be formed in a tapered or stepped tapered manner.Advantageously, the trench in each interlayer insulator layer separates(e.g., completely separates) one side of the interlayer insulator layerfrom metal layer(s) of a bond pad of the die (e.g., by about 4 microns),thereby preventing an interface (e.g., the interface I) between adjacentinterlayer insulator layers from extending to the metal layer(s) of thebond pad. This prevents moisture migration via the interface between theinterlayer insulator layers, which thereby prevents metal migration fromthe bond pad via the interface when a voltage is applied, therebypreventing a short circuit. The method 700 also includes the step offorming or applying a topcoat insulation layer 790, such as topcoatinsulation layer 590C-590L, over the interlayer insulator layer(s),including over the trench T. Optionally, the portion of the topcoatinsulation layer that extends over the trench T in the interlayerinsulator layer(s) extends to the location of a layer under theinterlayer insulator layer(s), such as a metal layer, an insulationlayer, or the substrate layer. The topcoat insulation layer isadvantageously impervious to moisture.

Advantageously, the examples described above inhibit (e.g., prevent)short circuiting of electronic components (e.g., bond pads) due to metalmigration via the interface between polymer interlevel dielectric layerscaused by moisture migration into the interface in the presence of anelectric field. Advantageously, this allows such a metal migration andmoisture migration problem to be solved without increasing the size ofthe die, or add to the manufacturing cost of the die. This solution alsoavoids the use of oxide based processes, which can add to the cost ofmanufacturing, and allows low dielectric constant material (e.g.,polyimide) to be used.

While certain embodiments of the inventions have been described, theseembodiments have been presented by way of example only, and are notintended to limit the scope of the disclosure. Indeed, the novel methodsand systems described herein may be embodied in a variety of otherforms. Furthermore, various omissions, substitutions and changes in thesystems and methods described herein may be made without departing fromthe spirit of the disclosure. The accompanying claims and theirequivalents are intended to cover such forms or modifications as wouldfall within the scope and spirit of the disclosure. Accordingly, thescope of the present inventions is defined only by reference to theappended claims.

Features, materials, characteristics, or groups described in conjunctionwith a particular aspect, embodiment, or example are to be understood tobe applicable to any other aspect, embodiment or example described inthis section or elsewhere in this specification unless incompatibletherewith. All of the features disclosed in this specification(including any accompanying claims, abstract and drawings), and/or allof the steps of any method or process so disclosed, may be combined inany combination, except combinations where at least some of suchfeatures and/or steps are mutually exclusive. The protection is notrestricted to the details of any foregoing embodiments. The protectionextends to any novel one, or any novel combination, of the featuresdisclosed in this specification (including any accompanying claims,abstract and drawings), or to any novel one, or any novel combination,of the steps of any method or process so disclosed.

Furthermore, certain features that are described in this disclosure inthe context of separate implementations can also be implemented incombination in a single implementation. Conversely, various featuresthat are described in the context of a single implementation can also beimplemented in multiple implementations separately or in any suitablesubcombination. Moreover, although features may be described above asacting in certain combinations, one or more features from a claimedcombination can, in some cases, be excised from the combination, and thecombination may be claimed as a subcombination or variation of a subcombination.

Moreover, while operations may be depicted in the drawings or describedin the specification in a particular order, such operations need not beperformed in the particular order shown or in sequential order, or thatall operations be performed, to achieve desirable results. Otheroperations that are not depicted or described can be incorporated in theexample methods and processes. For example, one or more additionaloperations can be performed before, after, simultaneously, or betweenany of the described operations. Further, the operations may berearranged or reordered in other implementations. Those skilled in theart will appreciate that in some embodiments, the actual steps taken inthe processes illustrated and/or disclosed may differ from those shownin the figures. Depending on the embodiment, certain of the stepsdescribed above may be removed, others may be added. Furthermore, thefeatures and attributes of the specific embodiments disclosed above maybe combined in different ways to form additional embodiments, all ofwhich fall within the scope of the present disclosure. Also, theseparation of various system components in the implementations describedabove should not be understood as requiring such separation in allimplementations, and it should be understood that the describedcomponents and systems can generally be integrated together in a singleproduct or packaged into multiple products.

For purposes of this disclosure, certain aspects, advantages, and novelfeatures are described herein. Not necessarily all such advantages maybe achieved in accordance with any particular embodiment. Thus, forexample, those skilled in the art will recognize that the disclosure maybe embodied or carried out in a manner that achieves one advantage or agroup of advantages as taught herein without necessarily achieving otheradvantages as may be taught or suggested herein.

Conditional language, such as “can,” “could,” “might,” or “may,” unlessspecifically stated otherwise, or otherwise understood within thecontext as used, is generally intended to convey that certainembodiments include, while other embodiments do not include, certainfeatures, elements, and/or steps. Thus, such conditional language is notgenerally intended to imply that features, elements, and/or steps are inany way required for one or more embodiments or that one or moreembodiments necessarily include logic for deciding, with or without userinput or prompting, whether these features, elements, and/or steps areincluded or are to be performed in any particular embodiment.

Conjunctive language such as the phrase “at least one of X, Y, and Z,”unless specifically stated otherwise, is otherwise understood with thecontext as used in general to convey that an item, term, etc. may beeither X, Y, or Z. Thus, such conjunctive language is not generallyintended to imply that certain embodiments require the presence of atleast one of X, at least one of Y, and at least one of Z.

Language of degree used herein, such as the terms “approximately,”“about,” “generally,” and “substantially” as used herein represent avalue, amount, or characteristic close to the stated value, amount, orcharacteristic that still performs a desired function or achieves adesired result. For example, the terms “approximately”, “about”,“generally,” and “substantially” may refer to an amount that is withinless than 10% of, within less than 5% of, within less than 1% of, withinless than 0.1% of, and within less than 0.01% of the stated amount. Asanother example, in certain embodiments, the terms “generally parallel”and “substantially parallel” refer to a value, amount, or characteristicthat departs from exactly parallel by less than or equal to 15 degrees,10 degrees, 5 degrees, 3 degrees, 1 degree, or 0.1 degree.

The scope of the present disclosure is not intended to be limited by thespecific disclosures of preferred embodiments in this section orelsewhere in this specification, and may be defined by claims aspresented in this section or elsewhere in this specification or aspresented in the future. The language of the claims is to be interpretedbroadly based on the language employed in the claims and not limited tothe examples described in the present specification or during theprosecution of the application, which examples are to be construed asnon-exclusive.

Of course, the foregoing description is that of certain features,aspects and advantages of the present invention, to which variouschanges and modifications can be made without departing from the spiritand scope of the present invention. Moreover, the semiconductor die withthe moisture barrier need not feature all of the objects, advantages,features and aspects discussed above. Thus, for example, those of skillin the art will recognize that the invention can be embodied or carriedout in a manner that achieves or optimizes one advantage or a group ofadvantages as taught herein without necessarily achieving other objectsor advantages as may be taught or suggested herein. In addition, while anumber of variations of the invention have been shown and described indetail, other modifications and methods of use, which are within thescope of this invention, will be readily apparent to those of skill inthe art based upon this disclosure. It is contemplated that variouscombinations or subcombinations of these specific features and aspectsof embodiments may be made and still fall within the scope of theinvention. Accordingly, it should be understood that various featuresand aspects of the disclosed embodiments can be combined with orsubstituted for one another in order to form varying modes of thediscussed moisture barrier in a semiconductor die.

What is claimed is:
 1. A method of making a semiconductor die, themethod 1 comprising: forming or providing a substrate layer; forming orapplying one or more metal layers over the substrate layer; forming orapplying a first polymer interlevel dielectric layer over the substratelayer and forming or applying a second polymer interlevel dielectriclayer over the first polymer interlevel dielectric layer to define aninterface therebetween, at least a portion of the first and secondpolymer interlevel dielectric layers being adjacent at least one of theone or more metal layers; forming a trench in the one or both of thefirst and second polymer interlevel dielectric layers and filling thetrench such that the interface between the first and second polymerinterlevel dielectric layers is separated from the one or more metallayers; and forming or applying a topcoat insulation layer over the oneor more metal layers and first and second polymer interlevel dielectriclayers, the topcoat insulation layer being impervious to moisture, thetrench inhibiting migration of moisture along the interface to the oneor more metal layers, thereby preventing metal migration from the one ormore metal layers along the interface.
 2. The method of claim 1 whereinfilling the trench includes filling the trench with one of: at least aportion of the topcoat insulation layer, at least a portion of one ormore metal layers, and at least a portion of another of the first andsecond polymer interlevel dielectric layers.
 3. The method of claim 1wherein the first and second polymer interlevel dielectric layers are afirst and second polyimide layers.
 4. The method of claim 1 wherein thetrench is formed in each of the two polymer interlevel dielectric layersin a stepped manner relative to each other.
 5. The method of claim 1wherein forming the trench includes etching one or both of the first andsecond polymer interlevel dielectric layers to form the trench.
 6. Themethod of claim 1 wherein the one or more metal layers are one or moreelectrodes of a bond pad.
 7. The method of claim 1 further comprisingforming or applying one or more insulation layers at least partiallyover the substrate layer.
 8. The method of claim 1 wherein forming thetrench includes tapering the trench toward the substrate layer.
 9. Themethod of claim 1 wherein the trench circumscribes a bond pad of thesemiconductor die defined at least in part by the one or more metallayers.
 10. A method of making a radiofrequency module, the methodcomprising: forming or providing a printed circuit board that includes asubstrate layer; forming or providing a semiconductor die comprising (a)forming or providing a substrate layer, (b) forming or applying one ormore metal layers over the substrate layer, (c) forming or applying afirst polymer interlevel dielectric layer over the substrate layer andforming or applying a second polymer interlevel dielectric layer overthe first polymer interlevel dielectric layer to define an interfacetherebetween, at least a portion of the first and second polymerinterlevel dielectric layers being adjacent at least one of the one ormore metal layers, (d) forming a trench in the one or both of the firstand second polymer interlevel dielectric layers and filling the trenchsuch that the interface between the first and second polymer interleveldielectric layers is separated from the one or more metal layers, and(e) forming or applying a topcoat insulation layer over the one or moremetal layers and first and second polymer interlevel dielectric layers,the topcoat insulation layer being impervious to moisture, the trenchinhibiting migration of moisture along the interface to the one or moremetal layers, thereby preventing metal migration from the one or moremetal layers along the interface; and mounting the semiconductor die onthe printed circuit board.
 11. The method of claim 10 wherein fillingthe trench includes filling the trench with at least a portion of thetopcoat insulation layer.
 12. The method of claim 10 wherein filling thetrench includes filling the trench with at least a portion of one ormore metal layers.
 13. The method of claim 10 wherein filling the trenchincludes filling the trench with at least a portion of another of thefirst and second polymer interlevel dielectric layers.
 14. The method ofclaim 10 wherein the first and second polymer interlevel dielectriclayers are a first and second polyimide layers.
 15. The method of claim10 wherein the trench is formed in each of the two polymer interleveldielectric layers in a stepped manner relative to each other.
 16. Themethod of claim 10 wherein forming the trench includes etching one orboth of the first and second polymer interlevel dielectric layers toform the trench.
 17. The method of claim 10 wherein the one or moremetal layers are one or more electrodes of a bond pad.
 18. The method ofclaim 10 further comprising forming or applying one or more insulationlayers at least partially over the substrate layer.
 19. The method ofclaim 10 wherein forming the trench includes tapering the trench towardthe substrate layer.
 20. The method of claim 10 wherein the trenchcircumscribes a bond pad of the semiconductor die defined at least inpart by the one or more metal layers.